1. Field of the Invention
This invention relates generally to host adapters for interfacing between I/O buses, and in particular to task suspension and resumption in multi-tasking host adapters.
2. Description of Related Art
Prior single chip host adapters have been single task devices. For example, U.S. Pat. No. 5,659,690, entitled "Programmably Configurable Host Adapter Integrated Circuit Including a RISC Processor," issued on Aug. 19, 1997 to Stuber et al., which is incorporated herein by reference, had a single data channel connecting a SCSI bus with a host computer bus. An on-chip RISC processor, sometimes called a sequencer, managed all of the modules on the chip through a set of registers.
This host adapter was multi-tasking in the sense that multiple commands, each for a different SCSI target, could be in process at any given time. However, hardware in the host adapter could execute only one task at a time, such as transferring data from one SCSI target to the host computer. The sequencer managed the one task until either completion or interruption of the task. Upon completion or interruption of the task, the sequencer disabled the hardware and then reconfigured the hardware for a different task.
Since the hardware on the host adapter chip could execute only one task at a time, the sequencer on the chip managed only the one active task at a time. Consequently, there were long periods of time in which the sequencer was idle, and was waiting for an event such as the end of the data transfer. While the sequencer was capable of performing other tasks, the hardware limitations made such performance unusable.
A subsequent host adapter integrated circuit had two independent data channels that were managed by a single on-chip sequencer. One of the data channels could be transferring data between the host computer and SCSI buses, while the other of the data channels could be transferring administrative data such as I/O command blocks, scatter/gather lists, or command completions notifications from or to the host computer. In this host adapter integrated circuit, rather than wait for an event associated with one of the two data channels, the sequencer waited in an idle loop for an event in either of the two data channels. This permitted the sequencer to concurrently supervise active tasks in both the channels, and to provide timely service when required.
The suspension and resumption of execution of a task by the sequencer is relatively simple, if execution can be suspended at only one point to await an event. In this case, when the sequencer reaches the point where execution of a first task can be suspended to wait for an event, the sequencer suspends execution of the first task by jumping to the idle loop, and looking for another task to execute. (It should be understood that the sequencer only executes firmware command lines. Therefore, stating that the sequencer jumps means that the sequencer executes a jump instruction in a firmware command line. Herein, any statement about a sequencer taking some action should be interpreted as the sequencer executing an instruction that results in the stated action.) When the sequencer is in the idle loop and the event associated with the first task is detected, the sequencer jumps back to the first task and resumes execution of that task.
The suspension and resumption of multiple tasks is more difficult to manage if there are multiple re-entry points associated with a single event. For example, typically, multi-tasking host-adapter firmware routines included a dedicated firmware routine for transfer of I/O command blocks, another dedicated firmware routine for transfer of scatter/gather lists, and yet another dedicated firmware routine for transfer of command completion notifications. Each of these routines enabled a DMA transfer to or from the host computer, and waited in the idle loop for completion of the transfer. The event, that caused the sequencer to resume execution of each of these routines, was a "DMA done" event. Each of these routines had a re-entry point for the DMA done event, and the sequencer had to decide which re-entry point to jump to in response to the DMA done event.
Tags are one way that is commonly used to determine which re-entry point to use. For example, in process 100 (FIG. 1), the sequencer executes a first group of instructions in first instruction set operation 101, e.g., initializes a data channel for a data transfer. The sequencer transfers processing from operation 101 to data available check 102. In data available check 102, the sequencer determines whether a first set of required data are available locally or need to be transferred over the I/O bus to the local memory. If the data are available locally, processing transfers to second instruction set operation 107.
However, if the data are not available locally, prior to jumping to the idle loop to wait for the data transfer, the sequencer transfers from data check 102 to write tag operation 103. In write tag operation 103, the sequencer executes an instruction that writes a unique tag, which identifies the routine, to scratch memory. After the tag is written, processing transfers to idle jump operation 104 in which the sequencer jumps to the idle loop as represented by idle loop node 105. Thus, to suspend execution of task 100, two instructions are required, the write instruction in operation 103, and the jump instruction in operation 104.
When the sequencer is in the idle loop and an event occurs that can have multiple re-entry points, the sequencer compares each of a set of possible tags for that event with the tag in scratch memory. When a match is found, the sequencer jumps to the re-entry point (program address) associated with the stored tag, e.g., re-entry point 106. Thus, in this instance, two instructions for each re-entry point, a compare and a jump to the re-entry point, were used. Alternatively, another sequencer used a single instruction that combined the compare and the jump in a single instruction. Nevertheless, in either instance, if there are multiple re-entry points, multiple instructions are required to determine the re-entry point. This basic process is repeated by operations 108 to 112 for the next set of data that are required.
This method of determining re-entry points has several disadvantages. The method requires a program instruction to write the tag to scratch memory, and this instruction must be executed each time the routine is suspended, which adds to the total execution time. When there are many points of execution suspension, there are many additional instructions that must be added to the firmware, which in turn increases the storage area required for the firmware. Typically, the die storage area available for firmware is limited and so it may be necessary to limit other firmware functionality to support saving the tags and still fit the firmware in the available storage area.
Also, the routine that processes the event must have at least one instruction for every firmware routine re-entry point that can be associated with that event. If there are multiple re-entry points, each must at least one instruction in the idle loop. This increases both the execution time and the required storage area.
In the worst case, the instruction with the matching tag is the last one in the list, and so all of the other instructions must be executed before the desired instruction is reached. Since the increased execution times and storage requirements are unattractive, a new method for suspending and resuming tasks is needed for multi-tasking host adapters.
In addition, while various schemes have been used for suspending and resuming task execution in multi-tasking microprocessors, these schemes have not been extended to host adapters because of the extensive hardware and/or firmware required to support the schemes. It is not practical to include a full-blown multi-tasking processor on the same die as the other circuits required for a host-adapter. Consequently, the task suspension and resumption solutions utilized in multi-tasking microprocessors are also unavailable.